Insulated gate power semiconductor devices

ABSTRACT

A trench-gate semiconductor device ( 100 ) has a trench network (STR 1 ), ITR 1 ) surrounding a plurality of closed transistor cells (TCS). The trench network comprises segment trench regions (STR 1 ) adjacent sides of the transistor cells (TCS) and intersection trench regions (ITR 1 ) adjacent corners of the transistor cells. As shown in FIG.  16  which is a section view along the line II-II of FIG.  11,  the intersection trench regions (ITR 1 ) each include insulating material ( 21 D) which extends from the bottom of the intersection trench region with a thickness which is greater than the thickness of the insulating material ( 21 B 1 ) at the bottom of the segment trench regions (STR 1 ). The greater thickness of the insulating material ( 21 D) extending from the bottom of the intersection trench regions (ITR 1 ) is effective to increase the drain-source reverse breakdown voltage of the device ( 100 ). The insulating material ( 21 D) which extends from the bottom of each intersection trench region (ITR 1 ) may extend upwards to thicken the insulating material at the corners of the cells (TCS) over at least part of the vertical extent of the channel-accommodating body region ( 23 ) so as to increase the threshold voltage of the device.

The present invention relates to insulated gate power transistorsemiconductor devices, and to methods of making such devices.

Vertical insulated gate field effect power transistor semiconductordevices are known comprising a semiconductor body having an active areawith a plurality of electrically parallel transistor cells, wherein eachtransistor cell has a source region and a drain region which areseparated by a channel-accommodating body region adjacent a peripheralinsulated gate structure.

Two types of such known vertical insulated gate power transistor devicesare the double-diffused metal-oxide-semiconductor form of verticalMOSFET device (VDMOS), and the trench-gate form of vertical MOSFETdevice. In a VDMOS device the gate structure has a planar gateinsulation layer on the top surface of the semiconductor body with thegate material thereon. In the on-state of this device current flows ineach transistor cell from the source region laterally under the gateinsulation layer in a conduction channel through the body regions into aperipheral drain drift region and then vertically through the draindrift region. In a trench-gate device the gate structure has a trenchwhich extends vertically through the body region with a gate insulationlayer at the vertical and bottom walls of the trench and gate materialin the trench within the gate insulation. In the on-state of this devicecurrent flows in each transistor cell only vertically from the sourceregion in a conduction channel next to the vertical gate insulationlayer through the body region into a drain drift region.

A desirable property of power transistors is to have a low on-stateresistance. Considering the two known power transistor devices justdescribed, it is known that when both these device structures are usedfor low and medium voltage power transistors, that it is with adrain-source breakdown reverse voltage of up to respectively about 50volts and about 200 volts, the on-state resistance of the device is to alarge extent dependent on the sum total of the conducting channelperipheries. Thus for a given size of the device, that is a given activetransistor cell area, a larger number of transistor cells in that activearea leads to a lower on-state resistance. A limitation in this respectfor the VDMOS device is that if the transistor cells are packed tooclose together by reducing the lateral extent of the peripheral draindrift region then the “Junction-FET” effect in this region willconstrict the vertical current flow path down to the drain. Thetrench-gate device does not have this “Junction-FET” limitation, so thatfor a given size of device the trench-gate structure can have moretransistor cells and a lower on-state resistance.

Another desirable property for power transistors is to have goodswitching performance, that is fast switching and low switching losseswhen the device is turned on and turned off. This is particularlyimportant where the power transistor is to be used in the output stageof a power supply, for example a voltage regulation module (VRM), whereit is continuously turned on and off at very high frequency. This goodswitching performance depends particularly on the device having a lowgate-drain capacitance. A limitation in this respect for the trench-gatedevice is the contribution to gate-drain capacitance added by the gateinsulation at the bottom of the trench. The VDMOS device does not havethis added contribution to gate-drain capacitance.

Although both on-sate resistance and gate-drain capacitance areimportant as discussed above, the present invention is more particularlyconcerned with devices having the possibility of very low on-stateresistance and so relates exclusively to trench-gate devices.

FIG. 1 of the accompanying drawings shows a schematic cross-section viewof a known trench-gate form of vertical MOSFET power transistorsemiconductor device 1. The device 1 comprises a silicon semiconductorbody 10 with top and bottom major surfaces 10 a, 10 b, firstconductivity type drain region 11 and a first conductivity type draindrift region 12.

FIG. 1 shows the lateral extent (the cell pitch) of one completetransistor cell TC and part of an adjacent transistor cell at eitherside of the cell TC. Two sections are shown of a peripheral insulatedgate structure G located in a trench 20 at the boundary between each twoadjacent transistor cells. The trench-gate structure G extendsvertically through a channel-accommodating second, opposite,conductivity, type body region 23 into the drain drift region 12, andhas silicon dioxide insulating material 21 at the vertical and bottomwalls of the trench 20 and gate material 22 in the trench 20 within theinsulating material 21. A source region 24, of the first conductivitytype, is present in each transistor cell under the top major surface 10a and adjacent the trench gate 21, 22. Thus the source region 24 and thedrain drift region 12 are vertically separated by thechannel-accommodating body region 23 adjacent the trench-gate 21, 22provided by the peripheral insulated gate structure G. This enables avertical conduction channel 23 a to be formed in the body portion 23when a suitable gate potential is applied to the gate material 22 in theon-state of the device 1, whereby current flows in a path in eachtransistor cell from the source region 24 vertically through theconduction channel 23 a to the drain drift region 12.

An insulating region 25 is provided over the gate structure G. Sourcemetallisation 18 contacting all of the source regions 24 is provided onthe first major surface 10 a over the insulating region 25 to provide asource electrode S. Although not shown, electrical connection to theinsulated gate structure G is provided by extending the insulatingmaterial 21 from the trenches 20 on to the top surface 10 a of thesemiconductor body 10 in an inactive area outside the active transistorcell area and extending the gate material 22 on to this top surfaceinsulating layer where it is contacted by metallisation to provide agate electrode. A metallisation layer 19 forms an ohmic contact with thedrain region 11 so as to provide a drain electrode D.

The cross-section view shown in FIG. 1 applies equally to each of twocell geometries which are known for trench-gate devices. FIG. 2 of theaccompanying drawings shows a plan view of an open-cell geometry havinga one-dimensionally repetitive pattern in which the trench-gates G1 areparallel stripes which each extend across the active area of the deviceat the peripheries of open stripe-shaped transistor cells TC1. In thiscase FIG. 1 shows a cross-section view along the line II-II of FIG. 2.FIG. 3 of the accompanying drawings shows a plan view of a closed-cellgeometry having a two-dimensionally repetitive pattern in which anetwork of trench-gates G2 over the active area of the device surroundsclosed polygonal transistor cells TC2. In this case FIG. 1 shows across-section view along the line III-III of FIG. 3 in which the closedcells are square shaped. Another commonly used closed polygonaltransistor cell is hexagonal shaped, a cross-section view of which wouldagain be as shown in FIG. 1. FIGS. 2 and 3 show the active cell areadimensions of the transistor cells for both the open-cell andclosed-cell geometries which are the trench width T, the semiconductormesa width M between trenches and the cell pitch P which is the sum of Tand M.

FIG. 4 of the accompanying drawings shows measurements which we havemade comparing the specific on-state resistance Rds,on (mOhm·mm²) of anopen stripe cell trench-gate device (curve 4A) and a closed square celltrench-gate device (curve 4B) as described with reference to FIGS. 1 and3 over a range of cell pitches from 2 micron to 7 micron. In both casesthe trench width is 0.4 micron at 2 micron cell pitch and about 0.6micron for pitches greater than 2 micron, and the semiconductor materialis {100} crystal orientation silicon. In these devices thechannel-accommodating body region 23 extends vertically to approximately0.7 micron below the upper surface 10 a of the semiconductor body, thedrain drift region 12 extends vertically to approximately 0.6 micronbelow the body region 23 and the trenches 20 are approximately 1.1micron deep. The combination of the trench depth and the drain driftregion depth are chosen to give a specified drain-source reversebreakdown voltage BVds for the device, in this case approximately 20volts. The combination of the body region depth and the drain driftdepth are chosen to give a low specific on-state resistance for thespecified drain-source breakdown voltage of the device. It is to benoted that the body region and drain drift region vertical profiles areshallower, and the corresponding values for Rds,on shown in FIG. 4 arelower, than for currently commercially available devices.

FIG. 4 shows that, for the same cell pitch, the closed square celldevices have a lower specific on-state resistance than the open stripecell devices. This is true down to about 2 micron cell pitch where thespecific resistance is approximately equal for the two types of device.However, a further advantage of closed-cell devices compared withopen-cell devices is that, particularly for low voltage devices, for agiven cell pitch the specific on-state resistance for a closed celldevice may be reduced by reducing the trench width whereas this is notpossible for an open cell device. The reason for this is that for aclosed cell device having a given cell pitch, reducing the trench widthincreases the channel perimeter and hence reduces the channelresistance; whereas for an open cell device reducing the trench widthdoes not increase the channel perimeter. This possibility for reducingthe specific resistance of closed cell devices is disclosed inInternational Patent Application published as WO-A-02/15254 (ourreference PHNL010059), the contents of which are incorporated herein byreference, which also discloses a suitable method for producing narrowtrenches in the range 0.4 micron to 0.1 micron; this method includingforming a silicon nitride cup on the semiconductor body top surface,forming curved spacers of silicon dioxide within the nitride cup whichare used to etch a window in the nitride cup and then etching a trenchusing the window in the nitride.

FIG. 5 of the accompanying drawings shows measurements which we havemade comparing the drain-source reverse breakdown voltage BVds of anopen stripe cell trench-gate device (curve 5A) with the BVds of a closedsquare cell trench-gate device (curve 5B) and a closed hexagonal celltrench-gate device (curve 5C) over a range of cell pitches from 2 micronto 7 micron. In all three devices the combination of the trench depthand the drain drift region depth dimensions is chosen to be the same asdescribed above for the devices as measured in FIG. 4 to give aspecified breakdown voltage BVds of 20 volts. Curve 5A shows that forthe open stripe cell devices BVds has the specified value of 20 voltsover the range of cell pitches, curve 5B shows that for the closedsquare cell devices BVds is reduced to about 17 volts over the range ofcell pitches, and curve 5C shows that for the closed hexagonal celldevices BVds is further reduced to about 15 volts over most of the rangeof cell pitches. Considering the results shown in FIGS. 4 and 5, thebreakdown voltage BVds could be increased for the closed cell devices byincreasing the drain drift depth but this would also undesirablyincrease the specific resistance.

It is therefore desirable to increase the drain-source reverse breakdownvoltage for closed cell trench-gate vertical power transistorsemiconductor devices without increasing the specific on-stateresistance as would occur in the manner mentioned just above. Theinvention seeks to address this issue using the inventors' appreciationof the properties of the corners of the transistor cells adjacent theintersection regions of the trench network for such closed cell devices,as will be discussed below.

FIGS. 6A and 7A of the accompanying drawings respectively show a planview of part of a trench network of the closed square transistor celldevice and of the closed hexagonal transistor cell device for whichbreakdown voltage BVds measurements have been shown in FIG. 5. As shownin FIG. 6A the trench network comprises a segment trench region STR1adjacent each one of four sides of a transistor cell TCS and anintersection trench region ITR1 (shown shaded) adjacent each one of thefour corners of the transistor cell TCS. As shown in FIG. 7A the trenchnetwork comprises a segment trench region STR2 adjacent each one of sixsides of a transistor cell TCH and an intersection trench region ITR2(shown shaded) adjacent each one of the six corners of the transistorcell TCH. The dotted square in FIG. 6A encloses the area around one ofthe intersection trench regions ITR1, this area is shown enlarged inFIG. 6B and a section view along the line I-I of FIG. 6B is shown inFIG. 6C. Likewise, the dotted triangle in FIG. 7A encloses the areaaround one of the intersection trench regions ITR2, this area is shownenlarged in FIG. 7B and a section view along the line I-I of FIG. 7B isshown in FIG. 7C. FIGS. 6C and 7C respectively show that the depth DI1,DI2 of the trench in the intersection regions is greater than the depthDS1, DS2 of the trench in the segment regions. An explanation for thetrench depth effect as shown in FIGS. 6C and 7C is as follows. Thetrench networks shown in FIGS. 6A and 7A are each produced using aconventional process in which a mask pattern is provided for the wholetrench network and there is one etching process for the whole network.In this case there is a loading effect which provides a more efficientsupply and hence a greater concentration of the etch chemicals, with aresulting greater trench depth, at the intersection trench regionscompared with the segment trench regions.

It will be noted that the intersection trench depth DI2 for thehexagonal closed cell device is shown in FIG. 7C to be greater than theintersection trench depth DI1 for the square closed cell device as shownin FIG. 6C. This will be the case if our following theory for theloading effect at the intersection trench regions is correct. Thistheory is that the loading effect is proportional to the number ofsegment trench regions at the periphery of an intersection trenchregion, four as shown in FIG. 6B and three as shown in FIG. 7B; and thatthe loading effect is inversely proportional to the area of anintersection trench region, T² for the square region ITR1 shown in FIG.6B where T is the trench width and 0.43T² for the equilateral triangleregion ITR2 shown in FIG. 7B where the trench width T is the same. Wehave made experimental observations using SEM photography which confirmqualitatively that the intersection trenches are deeper than the segmenttrenches for both the square cell network and the hexagonal cellnetwork. However, the limitations of SEM photography have prevented usfrom measuring the areas of the intersection trench regions for boththese networks and from quantitatively measuring the depths of theintersection trenches for both these networks, and so we have beenunable to confirm whether our loading effect theory described above iscorrect.

FIG. 8A of the accompanying drawings shows a cross-section view alongthe line I-I of both FIGS. 6A and 7A, that is showing part of the closedtransistor cell TCS/TCH and part of the segment trench region STR1/STR2adjacent a side of the cell for both the square closed cell device andthe hexagonal closed cell device. FIG. 8B of the accompanying drawingsshows a cross-section view along the line II-II of both FIGS. 6A and 7A,that is showing part of the closed transistor cell TCS/TCH and part ofthe intersection trench region ITR1/ITR2 adjacent a corner of the cell.FIGS. 8A and 8B show the greater depth of the intersection trenchregions ITR1/ITR2 compared with the depth of the segment trench regionsSTR1/STR2 as has been described above with regard to FIGS. 6B, 6C, 7Band 7C. The dashed lines in FIGS. 8A and 8B show the concentration ofequi-potential lines, for the same applied voltages, respectively at thebottom corner BC1 of the segment trench region STR1/STR2 at a side ofthe cell TCS/TCH and at the bottom corner BC2 of the intersection trenchregion ITR1/ITR2 at the corner of the cell TCS/TCH. These equi-potentiallines become closer at both bottom corners BC1 and BC2, but are closerat the bottom corner BC2 than at the bottom corner BC1 which implies ahigher electric field at the corner BC2 than at the corner BC1. An opencell geometry device such as shown in FIG. 2 has trench bottom cornerssuch as BC1 but does not have trench bottom corners such as BC2. Thehigher electric field at the cell corner bottom trench corner BC2 is amajor factor contributing to the lower drain-source breakdown voltageBVds shown in FIG. 5 for the closed cell devices compared with the opencell device. Also, the greater depth of intersection trench regions ITR2compared with the intersection trench regions ITR1 if it be the case,and the hexagonal cell having six corners compared with the square cellhaving four corners, are consistent with the breakdown voltage BVdsbeing lower for the hexagonal cell device (curve 5C) than for the squarecell device (curve 5B) as shown in FIG. 5.

Another factor, apart from the greater intersection trench depths, whichcontributes to lower drain-source reverse breakdown voltage BVds inclosed cell geometry devices compared with open cell devices is that inoperation, because the charge in the surrounding trench gate must beequal and opposite to the charge in the drain drift region for eachtransistor cell, there is a concentration of electric charge in thedrain drift region at the corners of the closed cells compared with atthe sides of the closed cells. This charge concentration leads to ahigher electric field at the corners of the closed cells which iseffective at the bottom corners of the intersection trench regions tolower the breakdown voltage BVds.

In FIGS. 8A and 8B the insulating material 21A2 at the vertical sides ofthe corners of the intersection trench regions ITR1/ITR2 is shown tohave the same thickness as the insulating material 21A1 at the verticalsides of the segment trench regions STR1/STR2; the thickness of theinsulating material 21B2 at the bottom of the intersection trenchregions ITR1/ITR2 is shown to have the same thickness as the insultingmaterial 21B1 at the bottom of the segment trench regions STR1/STR2; andthe vertical side thicknesses 21A1/21A2 are the same as the bottomthicknesses 21B1/21B2. These equal insulating material thicknesses areaccording to conventional practice.

FIG. 8C of the accompanying drawings exemplifies and illustrates anembodiment of the present invention, having insulating material 21C atthe bottom of the intersection trench regions ITR1/ITR2 with a thicknessgreater than that of the insulating material 21B1 at the bottom of thesegment trench regions STR1/STR2. As shown in FIG. 8C, the spacing ofthe equi-potential lines near the bottom trench corner BC2 at the cornerof the closed cell is increased as a result of the increased bottominsulation material thickness, thereby reducing the maximum electricfield at this corner BC2 and thereby increasing the drain-source reversebreakdown voltage BVds of the device.

Some simulation results on a trench-gate MOSFET device are given below.We were not able to do real three-dimensional simulations, but only sometwo-dimensional (2D) simulations. These 2D simulations are valid forstripe open cell structures and also for ideal (no variation in trenchdepth at intersections) hexagon closed cell structures. However thesesimulations could only be qualitatively be interpreted for square cellsin off-state (i.e. breakdown voltage) by examining severalcross-sections in each location in the cell and examining theequi-potential lines at breakdown condition.

In the simulations we used the same vertical doping profiles as for thedevices from which we obtained our experimental data as described withreference to FIGS. 4 and 5. Further, we assumed a pitch of 2.0 micronsand a trench width of 0.4 μm. Also, we assumed a trench depth of 1.2microns and basically imagined as if that is the actual depth of anintersection trench. The actual segment trench depth in the other partof the active area is 1.05 microns, measured by using SEM analysis. Alsoa gate-oxide thickness of 31 nm was used.

Some simulation results are shown in FIG. 9A of the accompanyingdrawings. This Figure shows the equi-potential lines in the device for adrain-source voltage of 17V. The breakdown voltage was here also 17V. Weconveniently took half the pitch size since reflective boundaryconditions (mirror) at the left and right edges are used in this devicesimulator. For the exactly the same device structure we increased theoxide thickness in the bottom of the device towards 0.35 micron, asshown in FIG. 9B of the accompanying drawings. The equi-potential linesare again taken for 17V drain-source voltage. The simulations predictthat the breakdown voltage of this structure is 23V, which is higherthan that of the structure shown in FIG. 9A. Consequently, when we havea locally deeper trench in the intersection areas than in the segmentareas as shown in FIG. 9A, the breakdown voltage reduces from about 20Vtowards 17V. However, when we use a thick oxide in the bottom of thetrench as shown in FIG. 9B the breakdown of the total device results in20V again, because the breakdown voltage of the structure shown in FIG.9B is 23V and is higher than that of the segment trench region. We didthe same simulations for hexagonal structures and obtained the sameresults for breakdown voltages as discussed above. It will be noted thatthe simulation results patterns of equi-potential lines distributionshown in FIGS. 9A and 9B correspond well with the equi-potential linepatterns shown respectively in FIGS. 8B and 8C.

Thus there is provided, in accordance with the present invention and asdefined in claim 1, a vertical power transistor trench-gatesemiconductor device having a trench network extending into asemiconductor body and surrounding a plurality of closed transistorcells, wherein the trench network comprises segment trench regionsadjacent sides of the transistor cells and intersection trench regionsadjacent corners of the transistor cells, wherein each transistor cellhas a source region and a drain region which are vertically separated bya channel-accommodating body region adjacent a segment trench region ateach side of the transistor cell, and wherein each segment trench regioncontains gate material separated from the semiconductor body byinsulating material at the vertical sides and at the bottom of thesegment trench region, wherein the intersection trench regions eachinclude insulating material which extends from the bottom of theintersection trench region with a thickness which is greater than thethickness of the insulating material at the bottom of the segment trenchregions, gate material being provided above the insulating material inthe intersection trench regions and bridging the gate material in thesegment trench regions, wherein the greater thickness of the insulatingmaterial extending from the bottom of the intersection trench regions iseffective to increase the drain-source reverse breakdown voltage of thedevice.

As mentioned above, in addition to the requirement for a powertransistor to have a low on-state resistance, it is also desirable for apower transistor to have a low gate-drain capacitance Cgd for goodswitching performance and a limitation in this respect for a trench-gatedevice is the contribution to gate-drain capacitance added by the gateinsulation at the bottom of the trenches. The contribution to the devicegate-drain capacitance by the insulation at the bottom of theintersection trench regions is reduced by the greater thickness of theinsulation in these regions in accordance with the invention asspecified above. The possibility of reducing the device gate-draincapacitance by increasing the thickness of the trench bottom insulationthroughout the trench network of a closed cell trench-gate device isalready known, for example from U.S. Pat. No. 4,992,390 and fromWO-A-2003/043089 (our reference PHNL020937). An advantageous optionalfeature of the present invention is therefore to have a combinationwherein the insulating material is thicker at the bottom of the trenchsegment regions than at the vertical sides of the trench segment regionsso as to reduce the gate-drain capacitance of the device, and whereinthe greater thickness of insulating material extending from the bottomof the intersection trench regions further reduces the gate-draincapacitance of the device.

In a device according to the present invention, with or without theoptional combination concerning gate-drain capacitance, the closedtransistor cells may each be rectangular (square or oblong) shaped witha said segment trench region adjacent each one of four sides of thecell. In this case each intersection trench region may have a squareshaped area, or each intersection trench region may have a cruciformshaped area. Another possibility is that the closed transistor cells mayeach be hexagonal shaped with a said segment trench region adjacent eachone of six sides of the cell.

The effect on the drain-source reverse breakdown voltage of theproperties of the corners of the transistor cells adjacent theintersection regions of the trench network of closed cell devices hasbeen discussed above, and it has been mentioned that, in operation,there is a concentration of electric charge, and hence a higher electricfield, at the corners of the closed cells compared with at the sides ofthe closed cells. This higher electric field at the corners of theclosed cells also has the effect of decreasing the threshold voltage Vthof the device, that is the gate-source voltage at which an electronchannel has formed through the body region and the device is in the onstate with current flow between the drain and source regions, as willnow be explained with reference to FIGS. 10A and 10B of the accompanyingdrawings.

FIG. 10A shows a horizontal cross-section view of part of a known closedsquare transistor cell device at the level of the channel-accommodatingbody region TCS (23) which has a segment trench region STR1 adjacenteach one of its four sides and an intersection trench region ITR1adjacent each one of the four corners of the body region TCS (23). Inoperation in the on state an electron channel 23 a is formed around theperimeter of the region 23. FIG. 10B shows the logarithmic drain-sourceelectron current Ids versus gate-source voltage V_(GS). Curve 10I showsan ideal curve due to the electron current excluding that at the cellcorners for which the device would have a threshold voltage V_(thI).Curve 10II shows the electron current Ids versus the gate-source voltageV_(GS) at the corners of the cell only. Due to the higher electric fieldat the corners of the closed cells, the current at the cell corners isparasitically higher than the current at the cell sides for the lowervalues of gate-source voltage and has a parasitic effect lower thresholdvoltage V_(thII). Curve 10III shows the total current by adding that inboth curves 10I and 10II. The threshold gate-source voltage for thedevice is determined by the lower parasitic value V_(thIl) which isundesirable because this results in a low threshold voltage with arelatively high specific on-resistance, and this is more the case withtrench-gate devices having the possibility of very low on-stateresistance where transistor cell pitch and size are particularly smalland properties of the cell corners have a greater effect. This parasiticthreshold voltage becomes particularly important for a small cell pitchless than about 3 micron.

FIG. 10C of the accompanying drawings shows a cross-section view alongthe line I-I of FIG. 10A, that is showing part of the closed transistorcell TCS and part of the intersection trench region ITR1 adjacent acorner of the cell, but modified in accordance with the invention in asimilar manner to FIG. 8C to have the insulating material 21C at thebottom of the intersection trench region ITR1 with a thickness greaterthan that of the insulating material 21B1 (see FIG. 8A) at the bottom ofthe segment trench region STR1, and additionally modified to exemplifyand illustrate a preferred feature of the invention which counteractsthe undesirable parasitic lowered threshold voltage discussed above.FIG. 10C shows that the part of the thicker trench bottom insulatingmaterial 21C which is nearest the corner of the adjacent transistor cellTCS extends upwards to thicken this gate insulating material at thecorner of the cell TCS over part of the vertical extent of thechannel-accommodating body region 23. Thus there is a lower portion 21A4of the vertical sidewall trench insulation at the corner of theintersection trench region ITR1 which is thickened compared with anupper portion 21A3 of the vertical sidewall insulation, this upperinsulation portion 21A3 having the same thickness as the vertical trenchside insulation thickness 21A1 and bottom trench insulation thickness21B1 in the segment trench regions STR1 (see FIG. 8A). FIG. 10C showsthat at a gate-source voltage V_(GS) equivalent to V_(thII) shown inFIG. 10B an electron channel 23 aII has formed adjacent the thinvertical corner insulation 21A3 while no electron channel has yet formedadjacent the thicker vertical corner insulation 21A4 and so the deviceis not turned on at the gate-source voltage V_(thII). The device isturned on when an electron channel is also formed adjacent the thickvertical corner insulation 21A4 at a higher gate-source voltage thanV_(thII). Thus the device has an increased threshold voltage which isdetermined by the thick insulation 21A4 which can approach the thresholdvoltage V_(thI) shown in FIG. 10B which would apply without the higherelectric field trench cell corner effect.

Thus, in accordance with an optional preferred feature of the presentinvention, at least that part of the insulating material which extendsfrom the bottom of each intersection trench region nearest the cornersof the adjacent transistor cells extends upwards to thicken theinsulating material at least at these corners over at least part of thevertical extent of the channel-accommodating region so as to increasethe threshold voltage of the device.

In accordance with the optional preferred feature defined in thepreceding paragraph, the insulating material in each intersection trenchregion which is thickened over at least part of the vertical extent ofthe channel-accommodating region may be so thickened only at aperipheral part of the area of the intersection trench region.Alternatively in accordance with this same optional preferred feature,the insulating material which extends from the bottom of eachintersection trench region may have the same thickness over the wholearea of the intersection trench region.

Preferably, in a device in accordance with the present invention thesemiconductor body is silicon and the insulating material at the bottomof the segment trench regions and the insulating material extending fromthe bottom of the intersection trench regions is silicon dioxide.

A preferred method of making a device in accordance with the presentinvention includes a first sequence of steps at the conclusion of whichthere are provided trenches for the intersection trench regions with theinsulating material which extends from the bottom of the trench regions,and in which there are provided empty trenches for the segment trenchregions, and a second sequence of steps at the conclusion of which thereis provided the insulating material at the vertical sides and bottom ofthe segment trench regions, and also there is provided the gate materialin the segment trench regions and above the insulating material in theintersection trench regions.

The above-defined first sequence of steps preferably includes etching afirst set of trenches in areas to be occupied by some of the segmenttrench regions and in areas to be occupied by the intersection trenchregions, providing the insulating material which will extend from bottomof the intersection trench regions in the final device within and alongthe whole length of the first set of trenches, etching a second set oftrenches in areas to be occupied by the remainder of the segment trenchregions, providing a different insulating material to fill the secondset of trenches and to cover the insulating material in the intersectiontrench regions, removing the insulating material from the segment trenchregions of the first set of trenches, and then removing the differentinsulating material.

Before describing exemplary embodiments of the present invention, it isnoted that International Patent Application published as WO-A-02/19432(inventor Hshieh) identifies the intersection trench regions of a closedcell trench gate device as undesirably contributing to the gate-draincapacitance of the device, particularly where there is a high celldensity for low on-resistance. Since there is no contribution to thedevice source-drain current in these intersection regions Hshiehproposes eliminating the trenches in these regions so as to remove thiscontribution to gate-drain capacitance, these intersection regions thenbeing occupied by the semiconductor body. The drain-source reversebreakdown voltage BVds of the device is not mentioned by Hshieh, and weconsider that the proposed structure results in trench bottom cornerswhich will decrease the breakdown voltage BVds of the device contrary tothe main object of the present invention. The matter of the devicethreshold voltage V_(th) also is not mentioned by Hshieh.

Exemplary embodiments of the present invention will now be described indetail with reference to the accompanying drawings, in which:

FIG. 1 shows a schematic cross-section view of a known trench-gateMOSFET as has been described above;

FIG. 2 shows a plan view of an open-cell geometry with the line II-IIindicating the cross-section of FIG. 1;

FIG. 3 shows a plan view of a closed square cell geometry with the lineIII-III indicating the cross-section of FIG. 1;

FIG. 4 shows our measurements of specific on-state resistance over arange of cell pitches for open and closed cell devices as shown in FIGS.1 to 3, as has been described above;

FIG. 5 shows our measurements of drain-source reverse breakdown voltageover a range of cell pitches for open and closed cell devices as shownin FIGS. 1 to 3, as has been described above;

FIGS. 6A and 6B show plan views of part of a trench network of a squareclosed cell device as measured in FIG. 5, and FIG. 6C shows a sectionview along the line I-I of FIG. 6B; as has been described above;

FIGS. 7A and 7B show plan views of part of a trench network of ahexagonal closed cell device as measured in FIG. 5, and FIG. 7C shows asection view along the line I-I of FIG. 7C, as has been described above;

FIG. 8A shows a section view along the line I-I of both FIGS. 6A and 7A,which shows part of the segment trench region adjacent a side of thecell, as has been described above;

FIG. 8B shows a section view along the line II-II of both FIGS. 6A and7A, which shows part of the intersection trench region adjacent a cornerof the cell, as has been described above;

FIG. 8C shows the view of FIG. 8B modified in accordance with anembodiment of the present invention which increases the drain-sourcereverse breakdown voltage of the devices, as has been described above;

FIGS. 9A and 9B show simulation results on section views similar tothose shown respectively in FIGS. 8B and 8C;

FIG. 10A shows a horizontal section view of part of a known closedsquare transistor cell device at the level of the channel-accommodatingbody region, as has been described above;

FIG. 10B shows drain-source current versus gate-source voltage at thecorners and at the sides of the device shown in FIG. 10A, as has beendescribed above;

FIG. 10C shows a cross-section view along the line I-I of FIG. 10A, butmodified in accordance with the present invention and further modifiedin accordance with a preferred optional feature of the present inventionso as to increase the threshold voltage of the device, as has beendescribed above;

FIG. 11 shows a plan view of a closed square transistor cell device inaccordance with one embodiment of the invention;

FIG. 12 shows a cross-section view along the line II-II shown in FIG.11;

FIGS. 13 and 14 respectively show cross-section views along the linesIII-III and IV-IV of FIG. 11 illustrating a modification of the deviceshown in FIGS. 11 and 12;

FIG. 15 shows a cross-section view along the line II-II of FIG. 11 butmodified with respect to FIG. 12 in accordance with a differentembodiment of the invention;

FIG. 16 shows a cross-section view along the line II-II of FIG. 11 butmodified with respect to FIG. 12 in accordance with a further differentembodiment of the invention;

FIG. 17 shows a plan view of a closed square transistor cell device witha modified cell layout in accordance with another embodiment of theinvention;

FIG. 18 shows a plan view of a closed square transistor cell device withintersection trench regions having a modified shape in accordance withanother embodiment of the invention;

FIG. 19 shows a horizontal cross-section view through the device of FIG.18;

FIGS. 20 to 26 illustrate steps included in a method of making a devicesubstantially in accordance with FIGS. 10 and 15;

FIGS. 27 to 29 illustrate modifications of part of the method shown inFIGS. 20 to 26 so as to make devices with different trench networklayouts; and

FIGS. 30A to 30C illustrate a modification of part of the methods shownin FIGS. 20 to 29 so as to make devices substantially in accordance withFIG. 15.

Referring now to FIG. 11 of the accompanying drawings there is shown aplan view of part of a closed square rectangular transistor celltrench-gate semiconductor device 100 in accordance with one embodimentof the present invention. A segment trench region STR1 is adjacent eachone of four sides of a transistor cell TCS and an intersection trenchregion ITR1 is adjacent each one of the four corners of the transistorcell TCS. The line I-I shown in FIG. 11 indicates a cross-section viewof the device through two segment trench regions STR1 at opposite sidesof a cell TCS and the mesa portion of the cell between those two segmentregions. This cross-section view along the line I-I will be the same asthe cross-section view shown in FIG. 1 for a conventional device and thedescription already given in relation to FIG. 1 can be taken as adescription of the view along line I-I of FIG. 10.

FIG. 12 of the accompanying drawings shows a cross-section view alongthe line II-II shown in FIG. 11, that is to say through and along asegment trench region STR1 and two intersection trench regions ITR1 atthe ends of the segment trench region. FIG. 12 shows regions of thesemiconductor body 10 of the device having a top surface 10 a referencedin the same manner as in FIG. 1, that is to say gate material 22 in thetrench regions STR1 and ITR1 above a drain drift region 12 and a drainregion 11; and there is also shown an insulating region 25 over the gatematerial 22, a source metallisation layer 18 and a drain metallisationlayer. As shown in FIG. 12 the depth DI1 of the trench in theintersection trench regions ITR1 is greater than the depth DS1 of thetrench in the segment trench regions in the same manner as has beenshown in FIG. 6C and for the reasons already explained in relation toFIG. 6C. A shown in FIG. 12 the insulating material 21C at the bottom ofthe intersection trench regions ITR1 has a thickness greater than thatof the insulating material 21B1 at the bottom of the segment trenchregions STR1 in the same manner as has already been shown in FIGS. 8Aand 8C, and the thicker intersection trench bottom insulation 21Cincreases the drain-source reverse breakdown voltage BVds of the deviceas has already been explained with reference to FIG. 8C. Thesemiconductor body 10 of the device 100 is silicon and the insulatingmaterial 21 at the bottoms and sides of the trench regions is silicondioxide. Although not shown in FIG. 12, the insulating material 21B1 atthe bottom of the segment trench regions STR1 has the same thickness asthe insulating material 21A1 (see FIG. 8A) at the vertical sides of thesegment trench regions STR1. Although not shown in FIG. 1, the gatematerial 22 in the intersection trench regions bridges the gate materialin the segment trench regions in that conventional device. FIG. 12 showsthat the thickened insulating material 21C at the bottom of theintersection trench regions ITR1 nevertheless also allows the gatematerial 22 provided above the insulating material 21C in theintersection trench regions ITR1 to bridge the gate material 22 in thesegment trench regions STR1. In the case of this device being a lowvoltage power transistor, that is with a drain-source breakdown voltageof up to about 50 volts, and having dimensions of the cell pitch, trenchwidth, trench depth, channel-accommodating body region (23 as shown inFIG. 1) depth and drain drift region depth designed for low specificon-state resistance Rds,on similar to the dimensions given above in thediscussion of FIG. 4, the intersection trench region bottom insulatingmaterial 21C thickness should be at least about 50 nm greater than thesegment trench region bottom insulating material 21B1 thickness in orderto provide a significant increase in the breakdown voltage BVds.

Referring now to FIG. 13 of the accompanying drawings, this shows across-section view along the line III-III of FIG. 11, that is showingpart of the transistor cell TCS and part of the segment trench regionSTR1 adjacent a side of the cell (a view similar to that shown in FIG.8A) but with a modification of the device 100 which is that theinsulating material 21B1′ at the bottom of the segment trench regionSTR1 is thicker than the insulating material 21A1 at the vertical sidesof the segment trench region STR1 so as to reduce the gate-draincapacitance of the device. Referring now to FIG. 14 of the accompanyingdrawings, this shows a cross-section view along the line IV-IV of FIG.11, that is showing part of the transistor cell TCS and part of theintersection trench region ITR1 adjacent a corner of the cell (a viewsimilar to that shown in FIG. 8C) but in a modified device as shown inFIG. 13 and therefore having a greater thickness of insulating material21C′ at the bottom of the intersection trench region ITR1 than thethickness of the segment trench bottom insulating material 21B1′ so asto further reduce the gate-drain capacitance of the device.

Referring now to FIG. 15 of the accompanying drawings there is shown across-section view which can be considered to be again along the lineII-II shown in FIG. 11 but modified with respect to FIG. 12 inaccordance with a different embodiment of the present invention. Asshown in FIG. 15 part of the insulating material 21C which extends fromthe bottom of each intersection trench region ITR1 is extended upwardsat two sides of the intersection trench region to form two verticalwalls 21A4 of insulating material having a height h above the bottominsulating material 21B1 in the segment trench regions STR1. The heighth is such that the walls 21A4 extend over at least that part of thevertical extent of the channel-accommodating body region 23, the bottomof the body region 23 being shown by a dashed lined in FIG. 15, whichdetermines the gate-source threshold voltage V_(th) of the device 100.Each vertical wall 21A4 of insulating material extends horizontallyfully across one side of a square area intersection trench region sothat the two walls 21A4 provided in each intersection trench areathicken the insulating material at a peripheral part of the area of thatintersection trench region ITR1 which includes a part nearest all fourcorners of the adjacent transistor cells TCS. That is to say there is athickening of the insulating material at these corners compared to thethickness which would be provided just by the vertical side walls of theinsulating material in the segment trench regions STR1. The effect ofthese vertical walls 21A4 of insulating material is to increase thethreshold voltage V_(th) of the device in the manner which has beendescribed and explained above in relation to the thick vertical cornerinsulation 21A4 shown in FIG. 10C.

The segment trench region bottom insulation layer 21B1 and theintersection trench region bottom insulation layer 21C as shown in FIG.15 can be thickened to decrease the device gate-drain capacitance in thesame manner as the insulation layers 21B1′ and 21C′ shown in FIGS. 13and 14.

Referring now to FIG. 16 of the accompanying drawings there is againshown a cross-section view which can be considered to be along the lineII-II shown in FIG. 11 but modified with respect to FIG. 12 inaccordance with a further different embodiment of the invention. Asshown in FIG. 16 insulating material 21D is provided in each of theintersection trench regions ITR1 which has the same thickness over thewhole area of the intersection trench region and extends from the bottomto the top of the intersection trench region. In this embodiment thewhole area thickened insulating material 21D need not extend to the topsurface 10 a of the semiconductor body 10 but will extend at least tothe height h as shown in FIG. 15 for the reason explained above withrespect to FIG. 15. The insulating material 21D provides the thickenedbottom trench insulating material to increase the drain-source reversebreakdown voltage BVds of the device as is achieved by the embodimentsshown in FIGS. 12 and 15, and also provides the thickened insulatingmaterial at the corners of the adjacent transistor cells TCS within thevertical extent of the channel accommodating body region 23 to increasethe threshold V_(th) of the device as is achieved by the embodimentshown in FIG. 15.

The embodiments of the present invention described above with referenceto FIGS. 11 to 16 of the accompanying drawings relate to a closed squaretransistor cell trench-gate semiconductor device. The features of havingthickened insulating material 21C, 21C′, 21D at the bottom of theintersection trench regions to increase the breakdown voltage BVds ofthe device and having thickened upward extensions 21A4, 21D of theintersection trench region insulating material at the corners of theadjacent transistor cells to increase the threshold voltage V_(th) ofthe device may also be used in other polygonal shaped closed transistorcell trench-gate devices. For example, considering the conventionalhexagonal cell device shown above in FIGS. 7A and 7B then, bysubstituting the hexagonal segment trench regions STR2 for STR1 and bysubstituting the intersection trench region ITR2 for ITR1, thecross-section views shown in FIGS. 12 to 16 may represent cross-sectionviews of a hexagonal cell device along the line I-I of FIG. 7B.

Referring now to FIG. 17 of the accompanying drawings there is shown aplan view of part of a closed square rectangular transistor celltrench-gate semiconductor device 101 in which the layout of thetransistor cells is modified compared with the layout of the cells TCSshown in FIG. 11. The cells TC3 as shown in FIG. 17 have a “shiftedsquares” layout, that is to say they are arranged in two sets ofalternate columns of square cells TC3, with one set of columns shiftedby half a cell pitch with respect to the other set. Each squaretransistor cell TC3 has a segment trench region STR3 extending alongeach of two sides of the cell across the width of a column between twointersection trench regions ITR3 each at a corner of the cell TC3. Eachsquare transistor cell TC3 also has a pair of segment trench regionsSTR4 extending along each of the two sides of the cell along the lengthof a column, each segment trench region STR4 being between anintersection trench region ITR3 at one corner of the cell and anintersection trench region ITR3 half way along one side of the cell.Referring back to FIGS. 6A to 6C, 7A to 7C, 8A and 8B and thedescription thereof in relation to the depth of intersection trenchregions compared with segment trench regions and the effect ondrain-source reverse breakdown voltage BVds, for intersection trenchregions of the same area in the two layouts, each intersection trenchregion ITR3 has only three segment trench regions at its peripherycompared with each intersection trench region ITR1 having four segmenttrench regions at its periphery so that with conventional single stagetrench network etching, we would expect the intersection trench regionsITR3 to be less deep than the intersection trench regions ITR1 whichwould tend to decrease the breakdown voltage BVds to a lesser extent.The two extra intersection trench regions ITR3 between the segmenttrench regions STR4 for each transistor cell TC3 will reduce the channelperimeter and hence increase the on-state resistance R_(ds)on of the“shifted squares” device 101 of FIG. 17 compared with the conventionalsquare cell device 100 of FIG. 6A by a small amount. The features of theinvention described above with reference to FIGS. 11 to 16 of havingthickened insulating material 21C, 21C′, 21D at the bottom of theintersection trench regions to increase the breakdown voltage BVds ofthe device and having thickened upward extensions 21A4, 21D of theintersection trench region insulating material at the corners of theadjacent transistor cells to increase the threshold voltage V_(th) ofthe device as described in relation to the conventional square celllayout device 100 of FIG. 11 may also be applied to the “shiftedsquares” cell layout device 101 of FIG. 17.

Referring now to FIG. 18 of the accompanying drawings there is shown aplan view of part of a closed square rectangular transistor celltrench-gate semiconductor device 102 in which the intersection trenchregions are modified compared with the intersection trench regions ofthe device 100 of FIG. 11. The intersection trench regions ITR5 of thedevice 102 have a cruciform shaped area with each leg of the cruciformshape extending a distance t along the side of a square transistor cellTCS. The segment trench regions STR5 of the device each have a lengthwhich, for the same mesa size of the cells, is an amount 2t less thanthe segment trench regions STR1 of the device 100 of FIG. 11. In oneembodiment of the invention having cruciform shaped intersection trenchregions ITR5 the insulating material at the bottom of the intersectiontrench regions ITR5 has a thickness greater than that of the insulatingmaterial at the bottom of the segment trench regions STR5 and across-section view of this embodiment along the line II-II of FIG. 18will look similar to FIG. 12 with the modification that, all otherdimensions being equal, the thickened bottom insulation layer 21C of theintersection trench region ITR5 will have a wider section and the bottominsulation layer 21B1 of the segment trench region STR5 will have anarrower section than the respective sections 21C and 21B1 shown in FIG.12. In another embodiment of the invention having cruciform shapedintersection trench regions ITR5 part of the thickened insulatingmaterial which extends from the bottom of each intersection trenchregion ITR5 nearest a corner of the four adjacent transistor cells TCSis extended upwards over part of the vertical extent of thechannel-accommodating body region in order to increase the thresholdvoltage V_(th) of the device in the manner as has been explained withreference to FIG. 15. This embodiment is illustrated in FIG. 19 of theaccompanying drawings which is a horizontal cross-section view throughthe device 102 at the vertical level of the channel-accommodating bodyregion 23 where the thickened bottom insulating material 21C in theintersection trench regions ITR5 extends upwards as vertical walls 21A4′each at a corner of a square transistor cell TCS and extending adistance t along a side of the square transistor cell. The abovedescription with reference to FIGS. 10A and 10B has explained how ahigher electric field at the corners of closed transistor cells in aconventional trench-gate device has the effect of parasiticallydecreasing the threshold voltage V_(th) of the device and the abovedescription with reference to FIG. 10C illustrates the basic idea ofcounteracting this undesirable parasitic lowered threshold voltage bythickening part of the vertical gate insulating material, portion 21A4as shown in FIG. 10C, in the intersection trench regions nearest thecorners of the adjacent transistor cells. The embodiment shown in FIG.19 substantially completely eliminates this parasitic threshold voltagelowering effect by ensuring that the electron channel 23 aIII for aspecific gate-source voltage is completely eliminated at the cellcorners, that is to say the channel 23 aIII is not present for adistance t from each corner of the cell. In another embodiment of theinvention having cruciform shaped intersection trench regions ITR5 thethickened insulating material which extends upwards from the bottom ofeach intersection trench region ITR5 extends upwards with the samethickness over the whole area of the intersection trench region in thesame manner as has been described with reference to FIG. 16 at least tothe height h as has been explained with reference to FIGS. 15 and 16. Itwill be appreciated that complete elimination of the electron channelfor a distance t from the corners of the transistor cell TCS by theinsulating material in the cruciform intersection trench regions as hasbeen described will reduce the channel perimeter of the device and soincrease the specific on-state resistance Rdson. The length t of eachleg of the insulation in the cruciform intersection trench regions needsto be optimised to balance this increase of on-state resistance againstthe beneficial effects on breakdown voltage BVds and threshold voltageV_(th).

The closed square rectangular cells TCS, TC3 described with reference toand as shown in FIGS. 11, 17 and 18 could instead be closed oblongrectangular cells, and the description of FIGS. 11 to 19 would equallyapply.

FIGS. 20 to 26 of the accompanying drawings illustrate steps included ina method of making a device substantially in accordance with FIGS. 11and 16, that is a closed rectangular cell transistor device havingsquare shaped area intersection trench regions and insulating materialin each intersection trench region which has the same thickness over thewhole area of the intersection trench region over the vertical extent ofthe channel-accommodating body region.

FIGS. 20A and 20B illustrate a silicon semiconductor body 10 at the endof a first step in the method, FIG. 20A being a plan view and FIG. 20Bbeing a cross-section view along the line I-I in FIG. 20A. An n+ drainregion substrate 11 is first provided and then an epitaxial n− draindrift region 12. Although not shown, acceptor implantation through thetop surface 10 a of the semiconductor body 10 is followed by donorimplantation and then annealing to form regions respectively for the ptype body regions 23 and the n+ type source regions 24 of the device asare shown in FIG. 1. A layer 30 of silicon dioxide, which may be formedusing tetraethyl orthosilicate (TEOS), is then provided on the topsurface 10 a of the semiconductor body 10 and a layer 31 of siliconnitride is provided on the layer 30. First windows are formed in theoxide 30 and nitride 31 layers by photolithography and successiveetching of these layers so as to provide a hard mask through which afirst set of parallel trenches TR1 is etched in areas to be occupied bysegment trench regions in a first direction and in areas to be occupiedby intersection trench regions.

FIG. 21A illustrates a plan view and FIG. 21B illustrates across-section view along the line I-I in FIG. 21A at the end of a secondstep in the method in which the trenches TR1 are filled with silicondioxide (TEOS) 32 which is then etched back to the top of the nitridelayer 31. The silicon dioxide 32 is the insulating material which willextend from the bottom of only the intersection trench regions in thefinal device, but at the end of this second step it is provided withinand along the whole length of the first set of parallel trenches TR1.

FIG. 22A illustrates a plan view, FIG. 22B illustrates a cross-sectionview along the line I-I in FIG. 22A and FIG. 22C illustrates across-section view along the line II-II in FIG. 22A at the end of athird step in the method. In this third step a second photolithographicmask is formed on the top surface of the regions 31, 32 through whichthese layers 31, 32 are etched to form a set of parallel second windowsin a second direction perpendicular to the first direction. Thesemiconductor body 10 is then etched through this set of second windowsto form a second set of parallel trenches TR2 in the areas to beoccupied by segment trench regions in the second direction. In thisetching of the semiconductor body the silicon dioxide 32 remains in thefirst set of trenches TR1 but has been etched back by a small depth TR1a in the intersection trench regions. The depth TR1 a is determinedduring the etching of the silicon dioxide layer 30 when creating thesecond set of windows to be used for etching the trenches TR2. Whenetching this second set of windows, the silicon dioxide (TEOS) layer 32at the intersections will automatically be etched to the depth TR1 a atthe same time.

FIG. 23A illustrates a plan view, FIG. 23B illustrates a cross-sectionview along the line I-I in FIG. 23A and FIG. 23C illustrates across-section view along the line II-II in FIG. 23A at the end of afourth step in the method. In this fourth step the second set ofparallel trenches TR2 is filled, and the etched back regions TR1 a whichare above the silicon dioxide 32 are also filled, with silicon nitride33 which is etched back so as not to cover the silicon dioxide 32 in thesegment trench regions of the first set of parallel trenches TR1. Thesegment trench regions of the first set of parallel trenches TR1 arethus filled with a first insulating material, silicon dioxide, and thesegment trench regions corresponding to the second set of paralleltrenches TR2 are filled with different insulating material, siliconnitride; the different insulating material also covering the firstinsulating material in the intersection trench regions.

FIG. 24A illustrates a plan view, FIG. 24B illustrates a cross-sectionview along the line I-I in FIG. 24A and FIG. 24C illustrates across-section view along the line II-II in FIG. 24A at the end of afifth step in the method. In this fifth step the silicon dioxide 32 isremoved by etching from the segment trench regions of the trenches TR1in the first direction. The silicon dioxide 32 which is in theintersection trench regions is not removed by this etching since it iscovered by silicon nitride 33.

FIG. 25A illustrates a plan view, FIG. 25B illustrates a cross-sectionview along the line I-I in FIG. 25A and FIG. 25C illustrates across-section view along the line II-II in FIG. 25A at the end of asixth step in the method. In this sixth step the silicon nitride 33 isremoved by etching from the segment trench regions TR2 between thetrenches TR1 in the second direction and from over the silicon dioxide32 in the intersection trench regions.

The above-described six steps thus provide a first sequence of steps atthe conclusion of which there are provided trenches for the intersectiontrench regions with the insulating material 32 which extends from thebottom of the intersection trench regions, and in which there areprovided empty trenches TR1, TR2 in the first direction and the second,perpendicular direction for the segment trench regions. An alternativefirst sequence of steps which would arrive at this same conclusion wouldbe to etch the whole trench network consisting of the segment trenchregions and the intersection trench regions, then to fill the wholetrench network with silicon dioxide (TEOS) and then etch the segmenttrench regions empty with a mask which covers the intersection trenchregions. This will result in the intersection trench regions beingdeeper than the segment trench regions. This alternative first sequenceof steps would allow the intersection trench regions to contain aninsulating material different from instead of the same as the gateinsulating material to be provided in the segment trench regions.

FIG. 26A illustrates a plan view, FIG. 26B illustrates a cross-sectionview along the line I-I in FIG. 26A and FIG. 26C illustrates across-section view along the line II-II in FIG. 26A at the conclusion ofa second sequence of steps which follows the first sequence of stepsdescribed above. In this second sequence of steps insulating material,silicon dioxide, 34 is provided at the bottom walls 21B1 and verticalside walls 21A1 of the segment trench regions TR1, TR2. Then gatematerial 22, doped polycrystalline silicon, is provided in the segmenttrench portions TR1, TR2 to provide segment trench-gate regions STR1 andabove the silicon dioxide insulating material 32 in the intersectiontrench regions so as to bridge the gate material 22 in the segmenttrench regions TR1, TR2. FIG. 26C substantially corresponds to FIG. 16described above with the insulating material 32 shown in FIG. 26Ccorresponding to the insulating material 21D shown in FIG. 16.

After the second sequence of steps just described with reference toFIGS. 26A to 26C, further processing is performed to insulate the topsurface of the gate material 22 and etch the silicon dioxide layer 30 sothat source metal may contact the source and body regions at the topsurface 10 a. One method could be to deposit an additional silicondioxide layer (TEOS) on top of the structure shown in FIGS. 26A to 26Cand then use a mask to etch through this additional silicon dioxidelayer and the silicon dioxide layer 30.

It will be noted that FIG. 16 shows the intersection trench regions ITR1having a greater depth than the segment trench regions STR1, which isconsistent with the conventional process of etching the whole trenchnetwork in a single stage as discussed and explained with respect toFIGS. 6B and 6C. By contrast, FIG. 26C shows the intersection trenchregions ITR1 having the same depth as the segment trench regions STR1.This equality of depth is made possible by etching the trench network intwo separate stages as in the first and third steps described above. Itis also possible that the trenches TR1 etched in the first step will bedeeper than the trenches TR2 etched in the third step, in which case theintersection trench regions ITR1 will be deeper than the segment trenchregions STR2 etched in the third step. If the method is modified so thatin the second step described above with reference to FIGS. 21A, B and Cthe trenches TR1 are only partly filled then this will result in theintersection trench regions ITR1 being partly filled in accordance withthe insulation layer 21C in the embodiment of the invention shown inFIG. 12.

FIG. 27 to 29 illustrate modifications of the method described withreference to FIGS. 20 to 26 having regard to the pattern used foretching the first set of trenches TR1 in the first step in areas to beoccupied by some of the segment trench regions of the device and inareas to be occupied by the intersection trench regions, and havingregard to the pattern used for etching the second set of trenches TR2 inthe third step in areas to be occupied by the remainder of the segmenttrench regions of the device.

FIGS. 27A to 27C show patterns used for producing a “shifted squares”trench network as shown in FIG. 17. FIG. 27A shows the trench patternTR11 for some of the segment trench regions and the square shapedintersection trench regions, shown shaded as TR11I, used in the firststep. FIG. 27B shows the trench pattern TR21 for the remainder of thesegment trench regions and which also extends over the intersectiontrench regions, shown shaded as TR21I, used in the third step. Theoverlap positioning of these two patterns is shown in FIG. 27C.

FIGS. 28A to 28C show patterns used for producing a cruciform shapedintersection trench network as shown in FIG. 18. FIG. 28A shows thetrench pattern TR12 for some of the segment trench regions and thecruciform shaped intersection trench regions, shown shaded as TR12I,used in the first step. FIG. 28B shows the trench pattern TR22 for theremainder of the segment trench regions and which also extends over theintersection trench regions, shown shaded as TR22I, used in the thirdstep. The overlap positioning of these two patterns is shown in FIG.28C.

FIG. 29A to 29C show patterns used for producing a hexagonal closed celltrench network. FIG. 29A shows the trench pattern TR13 for some of thesegment trench regions and the triangular shaped intersection trenchregions, shown shaded as TR13I, used in the first step. FIG. 29B showsthe trench pattern TR23 for the remainder of the segment trench regionsand which also extends over the intersection trench regions, shownshaded as TR23I, used in the third step. The overlap positioning ofthese two patterns is shown in FIG. 29C.

FIGS. 30A to 30C are cross-section views through the first trenches TR1which have been formed according to the first step described above withreference to FIGS. 20A and 20B, but in which the second step describedabove with reference to FIGS. 21A and 21B is modified by a stagedprocess so that instead of this second step ending with the trenches TR1completely filled with silicon dioxide (TEOS) it ends with the trenchesfilled with a composite structure which will enable a device to beformed substantially in accordance with FIG. 15 shown and describedabove. FIG. 30A illustrates a first stage of this modified second stepin which a layer of silicon dioxide (TEOS) 32A is formed at the bottomand vertical side walls of the trenches TR1 and also extends up and overthe silicon dioxide layer 30 and silicon nitride layer 31 on the topsurface 10 a of the semiconductor body 10. The thickness of this layer32A is made to correspond to the thickness required for the trenchbottom insulation 21C and vertical side wall insulation 21A4 asdescribed and shown above with reference to FIG. 15. FIG. 30Billustrates a second stage of this modified second step in whichpolycrystalline silicon 35A is deposited and then etched back to thelevel shown which is a determined height above the bottom of thechannel-accommodating channel region 23 as shown by the dashed line inFIG. 30B, and in which the silicon dioxide (TEOS) layer 32A is thenetched back to form the cup shaped region 32B level with the top of thepolycrystalline silicon 35A as shown in FIG. 30B. FIG. 30C illustrates athird stage of this modified second step in which a thin layer ofsilicon dioxide 32C is provided at the vertical side walls of the trenchTR1 in order to prevent gate-source leakage; then polycrystallinesilicon 35B is deposited in the trench TR1 and etched back to the top 10a of the body 10; and then a silicon dioxide layer 36 is provided on topof the polycrystalline silicon 35B within the window in the maskprovided by the layers 30, 31. The method then proceeds in the samemanner as steps three and four described above with respect to FIGS. 22and 23. The fifth step described above with respect to FIG. 24 ismodified to empty the segment trench regions of the trenches TR1 outsidethe intersection trench regions by successively removing from those TR1segment trench regions the regions 36, 35B and 35A, 32C and 32B shown inFIG. 26C. The method then proceeds in the same manner as described abovewith respect to FIGS. 25 and 26.

From reading the present disclosure, other variations and modificationswill be apparent to persons skilled in the art. Such variations andmodifications may involve equivalent and other features which arealready known in the art, and which may be used instead of or inaddition to features already described herein.

Although Claims have been formulated in this Application to particularcombinations of features, it should be understood that the scope of thedisclosure of the present invention also includes any novel feature orany novel combination of features disclosed herein either explicitly orimplicitly or any generalisation thereof, whether or not it relates tothe same invention as presently claimed in any Claim and whether or notit mitigates any or all of the same technical problems as does thepresent invention.

Features which are described in the context of separate embodiments mayalso be provided in combination in a single embodiment. Conversely,various features which are, for brevity, described in the context of asingle embodiment, may also be provided separately or in any suitablesubcombination. The Applicants hereby give notice that new Claims may beformulated to such features and/or combinations of such features duringthe prosecution of the present Application or of any further Applicationderived therefrom.

1. A vertical power transistor trench-gate semiconductor device having atrench network extending into a semiconductor body and surrounding aplurality of closed transistor cells wherein the trench networkcomprises segment trench regions adjacent sides of the transistor cellsand intersection trench regions adjacent corners of the transistorcells, wherein each transistor cell has a source region and a drainregion which are vertically separated by a channel-accommodating bodyregion adjacent a segment trench region at each side of the transistorcell, and wherein each segment trench region contains gate materialseparated from the semiconductor body by insulating material at thevertical sides and at the bottom of the segment trench region whereinthe intersection trench regions each include insulating material whichextends from the bottom of the intersection trench region with athickness which is greater than the thickness of the insulating materialat the bottom of the segment trench regions, gate material beingprovided above the insulating material in the intersection trenchregions and bridging the gate material in the segment trench regions,wherein the greater thickness of the insulating material extending fromthe bottom of the intersection trench regions is effective to increasethe drain-source reverse breakdown voltage of the device
 2. A device asclaimed in claim 1, wherein the insulating material is thicker at thebottom of the trench segment regions than at the vertical sides of thetrench segment regions so as to reduce the gate-drain capacitance of thedevice and wherein the greater thickness of insulating materialextending from the bottom of the intersection trench regions furtherreduces the gate-drain capacitance of the device.
 3. A device as claimedin claim 1, wherein the closed transistor cells are each rectangularshaped with a said segment trench region adjacent each one of four sidesof the cell.
 4. A device as claimed in claim 3, wherein the closedtransistor cells are square shaped.
 5. A device as claimed in claim 3wherein each intersection trench region has a square shaped area.
 6. Adevice as claimed in claim 3, wherein each intersection region has acruciform shaped area.
 7. A device as claimed in claim 1, wherein theclosed transistor cells are each hexagonal shaped with a said segmenttrench region adjacent each one of six sides of the cell.
 8. A device asclaimed in claim 1, wherein at least that part of the insulatingmaterial which extends from the bottom of each intersection trenchregion nearest the corners of the adjacent transistor cells extendsupwards to thicken the insulating material at least at these cornersover at least part of the vertical extent of the channel-accommodatingbody region so as to increase the threshold voltage of the device.
 9. Adevice as claimed in claim 8, wherein the insulating material in eachintersection trench region which is thickened over at least part of thevertical extent of the channel-accommodating region is so thickened onlyat a peripheral part of the area of intersection trench region.
 10. Adevice as claimed in claim 8, wherein the insulating material whichextends from the bottom of each intersection trench region has the samethickness over the whole area of the intersection trench region.
 11. Adevice as claimed in claim 1, wherein the semiconductor body is siliconand wherein the insulating material at the bottom of the segment trenchregions and the insulating material extending from the bottom of theintersection trench regions is silicon dioxide.
 12. A method of making adevice as claimed in claim 1, the method including a first sequence ofsteps at the conclusion of which there are provided trenches for theintersection trench regions with the insulating material which extendsfrom the bottom of the intersection trench regions, and in which thereare provided empty trenches for the segment trench regions, and a secondsequence of steps at the conclusion of which there is provided theinsulating material at the vertical sides and bottom of the segmenttrench regions, and also there is provided the gate material in thesegment trench regions and above the insulating material in theintersection trench regions.
 13. A method as claimed in claim 12,wherein the first sequence of steps includes etching a first set ofparallel trenches in areas to be occupied by some of the segment trenchregions and in areas to be occupied by the intersection trench regionsproviding the insulating material which will extend from bottom of theintersection trench regions in the final device within and along thewhole length of the first set of trenches etching a second set oftrenches in areas to be occupied by the remainder of the segment trenchregions providing a different insulating material to fill the second setof trenches and to cover the insulating material in the intersectiontrench regions removing the insulating material from the segment trenchregions of the first set of trenches and then removing the differentinsulating material